The present invention relates to a memory patching system for altering information contained in Read Only Memories (ROM's) used in electrical computers and processors.
Unalterable ROM's are used in computers, processors and other such applications requiring the storage of permanent type information. The ROM's are efficient unalterable information storage devices, however, there is a problem when it becomes necessary to change the stored information because of, for example, information code deficiencies or updating. This problem could be solved by replacing a particular ROM with a new ROM programmed with the correct or updated information. However, this solution is neither feasible nor economical.
U.S. Pat. Nos. 3,588,830 and 3,755,791 disclose error correcting schemes for memory systems, and their purposes are to correct bad data bits to improve reliability, not alter the information, namely, the machine code data. U.S. Pat. No. 4,032,765 discloses a method of correcting ROM output by altering individual bits of the output by controlling AND/OR gates on the output, and a "patch package" is used to provide the data for changes. This technique is targeted for ROM fabrication but only provides a single ROM address correction only. U.S. Pat. No. 4,047,163 discloses a technique for implementation of fault tolerant cells within addressable arrays for semiconductor memories, but it is only for reliability and yield increase of memory IC's. U.S. Pat. No. 4,051,460 is another technique for error correction within semiconductor memory chips, but it does not apply to alteration of machine code data. U.S. Pat. No. 4,070,651 discloses a technique utilizing a PROM and counter scheme for correcting errors in magnetic bubble memory systems whereby another loop output is substituted for a defective one as necessary. U.S. Pat. No. 3,331,058 is a technique for correcting permanent errors in thin film magnetic memories. It is targeted at reliability and yield increase of devices but not data alteration after installation. U.S. Pat. No. 4,028,678 discloses a technique based on hardware that provides interception of a processor address and substitution of data as required. Its purpose is to correct bad ROM program data, but it is very limited in the number of locations correctable (8 maximum). In addition, only a single location may be altered at one time. U.S. Pat. No. 4,028,679 represents an expansion of the above U.S. Pat. No. 4,028,678, and the number of patches is increased through the addition of address bits to an auxiliary memory. Even though the number of patches is increased, it is limited. U.S. Pat. No. 4,028,683 is a refinement of the above U.S. Pat. No. 4,028,679 whereby a counter is added to provide even more bits of address to the auxiliary memory, however, the number of patches is not enough. U.S. Pat. No. 4,028,684 discloses a memory patching circuit that has ability to correct mistakes of data already present.